An application specific integrated circuit (ASIC) is an integrated circuit designed or customized for a specific use or task. Generally, a customer or client requests a manufacturer or ASIC design center to fabricate an ASIC to perform specific logic. The customer may provide a “netlist,” which represents the desired logic operation for the application, or some other representation of the logic for performing the desired task to a designer or engineer. The designer or engineer takes the customer's logic and synthesizes it into gate logic. This gate logic is then placed and routed to form a physical design of the chip, which can take, e.g., many weeks to months to complete.
During the placing and routing procedure, it is not unusual for the customer to request engineering changes for the logic, e.g., in an effort to improve the ASIC functionality. In this regard, it can be difficult, after logic synthesis and the initial physical design process, to change the placed and routed gate logic. As a result, incorporating the engineering changes into the ASIC may generally result in a very complicated and lengthy ordeal for the designer/engineer. Moreover, gate logic cannot generally simply be replaced, since changing gate logic can result in different timing characteristics between the gates that must also be considered in the new gate logic.
The underlying obstacles to putting in engineering changes to a chip have for a long time plagued designers. From distilling down the minimal change in a netlist (when the change was made to register transfer logic (RTL)) to rewiring gates on an existing placement the change is always a timely complicated process and does not lend itself to automation.
Functional logic blocks (FLBs) can be used in place of standard cell logic gates in order to enable easy changes to functional blocks with wire, as discussed in commonly owned U.S. application Ser. No. 11/838,929 filed Aug. 15, 2007, the disclosure of which is expressly incorporated by reference herein in its entirety. The function can be implemented with a separate library of simple logic, e.g., NAND gates and NOR gates, where the simple logic blocks are built up from higher complexity block, e.g., AOIs with inputs tied up and down inside the library block to create the simpler logic function. This would enable additional logic that can be easily changed in the existing logic path.